1. Field of the Invention
The invention relates in general to a memory, and more particularly to a memory with shielding effect.
2. Description of the Related Art
FIG. 1A is a schematic diagram illustrating an equivalent circuit of a conventional read only memory. The memory includes multiple memory cell columns (C) that are connected to the sub bit lines adjacent to them. Every memory cell column (C) can be enabled through the word lines (WL0-WLm), and has m+1 memory cells where m is a positive integer. Every memory cell is used to store data of either 1 or 0. Every memory cell can be a transistor for which a threshold voltage Vt is embodied according to its to-be-stored data at manufacturing. By the control switches MB0-MB7, the block word line (BWL) can enable this memory block. The switches MS0, MS1, and MS3 determine whether the primary bit lines SB0, SB1, and SB2 are electrically connected to the sense amplifier control unit 130. The switches MS0, MS1, MS2 are controlled by the control signals SB0, SB1, and SB2 respectively. The primary bit lines SB0, SB1, SB2 are also electrically connected to the bit line control unit 110 by which the bit lines can be pulled high or pulled low. The ground lines GL0-GL3 are electrically connected to the ground line control unit 120 by which the ground lines can be pulled high or pulled low. By controlling the word lines WL0-WLm, the ground line G, the primary bit line SB, and the selective bit lines BRT and BLT, a cell which is to be read can be determined.
The operation of the read only memory aforementioned can be further explained by showing an example of reading a memory cell C5. When the word line WL, the control signal YS1, and the select signal BRT have been enabled, and additionally the ground line GL1 has been discharged to the ground level, the current flows to the ground line GL1 through the primary bit line SB1. The value stored in the memory cell can be obtained from amplifying the current of the primary bit line SB1 by the sense amplifier control unit.
Please note that at this moment, the primary bit line SB0 is floating and therefore the electric charges in SB0 also flows to GL1. Consequently, the current of SB1 is decreased and this may cause data misread. Therefore, there has to be a shielding mechanism to prevent from data misread.
The conventional memory uses the bit line control unit 110 and the ground line control unit 120 to create a shielding effect. In the example above, if the primary bit line is pulled low by the bit line control unit 110, a shielding mechanism, which can prevent the current flowing from primary bit line SB0 to ground line GL1, is created in the left hand side of ground line GL1; furthermore if the ground line control unit 120 pulls the ground lines GL2 and GL3 high, and the bit line control unit 110 pulls the primary bit line SB2 high, a shielding mechanism, that can prevent data misread, is created in the right hand side of the primary bit line SB1.
However, the shielding mechanism created by the bit line control unit 110 and the ground line control unit 120 complicate the logic of the circuit board. In addition, it is still possible to cause current leakage and data misread in this mechanism, the reason is stated below.
Please refer to FIG. 1B, which schematically shows the current flow of FIG. 1A. Every sub bit line is formed by buried diffusion layers and will inevitably cause resistance effect. When reading memory cell column C5, current I1 of the primary bit line SB1 flows downwards into the buried diffusion layers and the voltage at node N1 is assumed to be V1. The ground line GL2, which is controlled by the ground line control unit 120, is acting as a shielding mechanism. Current 12 flows upwards into the buried diffusion layers and the voltage at node N2 is assumed to be V2. Currents 11 and 12 are in different directions. When current 12 arrives at node N2, the buried diffusion layers which current 12 flows through is longer than that of current 11 arriving at node N1, and therefore voltage V2 at node N2 is smaller than voltage V1 at node N1. Due to the voltage difference between nodes N1 and N2, current leakage occurs and hence the correctness of the data is affected.